2237 search results - page 49 / 448 » Architectural design and evaluation of an efficient Web-craw... |
226
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HPCA
2003
IEEE
16 years 6 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
164
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ICPADS
2005
IEEE
15 years 12 months ago
2005
IEEE
The evaluation of QoS requirements is one of the critical functions that span both the design and the run-time phases of QoS management. This paper presents an architecture for Qo...
164
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FPL
2000
Springer
15 years 10 months ago
2000
Springer
Coarse-grain reconfigurable architectures have been a matter of intense research in the last few years. They promise to be more adequate for computational tasks due to their better...
182
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FPL
2006
Springer
15 years 10 months ago
2006
Springer
The recent development of Platform-FPGA or FieldProgrammable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potent...
169
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VLSISP
2008
15 years 4 months ago
2008
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...