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CODES
2006
IEEE
16 years 7 days ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
CASES
2009
ACM
16 years 21 days ago
Hardware evaluation of the Luffa hash family
Efficient hardware architectures for the Luffa hash algorithm are proposed in this work. We explore different tradeoffs and propose several architectures, targeting both compac...
Miroslav Knezevic, Ingrid Verbauwhede
SDL
2003
147views Hardware» more  SDL 2003»
15 years 7 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
ICSE
2008
IEEE-ACM
16 years 6 months ago
An ontology-driven software architecture evaluation method
Software architecture evaluation has a crucial role in the life cycle of software intensive systems. In this paper we propose an approach to empower a software architecture evalua...
Aida Erfanian, Fereidoun Shams Aliee
ICCS
2001
Springer
15 years 10 months ago
GEA: A Complete, Modular System for Generating Evaluative Arguments
This paper presents a system for generating user tailored evaluative arguments, known as the Generator of Evaluative Arguments (GEA). GEA design is based on a pipelined architectur...
Giuseppe Carenini