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CSC
2010
15 years 4 months ago
An Evaluation of Parallel Knapsack Algorithms on Multicore Architectures
Emergence of chip multiprocessor systems has dramatically increased the performance potential of computer systems. Since the amount of exploited parallelism is directly influenced ...
Hammad Rashid, Clara Novoa, Apan Qasem
VLSISP
2008
129views more  VLSISP 2008»
15 years 6 months ago
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, O...
CODES
2004
IEEE
15 years 10 months ago
Efficient exploration of on-chip bus architectures and memory allocation
Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and map...
Sungchan Kim, Chaeseok Im, Soonhoi Ha
IISWC
2008
IEEE
16 years 18 days ago
A workload for evaluating deep packet inspection architectures
—High-speed content inspection of network traffic is an important new application area for programmable networking systems, and has recently led to several proposals for high-per...
Michela Becchi, Mark A. Franklin, Patrick Crowley
MOBIHOC
2009
ACM
16 years 6 months ago
Efficient resource management in OFDMA Femto cells
Femto cells are a cost-effective means of providing ubiquitous connectivity in future broadband wireless networks. While their primary purpose has been to improve coverage in curr...
Karthikeyan Sundaresan, Sampath Rangarajan