Sciweavers

2237 search results - page 265 / 448
» Architectural design and evaluation of an efficient Web-craw...
Sort
View
DAC
2009
ACM
16 years 7 months ago
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-K...
CN
2010
130views more  CN 2010»
15 years 4 months ago
CoreCast: How core/edge separation can help improving inter-domain live streaming
The rapid growth of broadband access has popularized multimedia services, which nowadays contribute to a large part of Internet traffic. Among this content, the broadcasting of li...
Loránd Jakab, Albert Cabellos-Aparicio, Tho...
JIRS
2007
108views more  JIRS 2007»
15 years 6 months ago
Task-based Hardware Reconfiguration in Mobile Robots Using FPGAs
This paper presents a methodology for the realization of intelligent, task-based reconfiguration of the computational hardware for mobile robot applications. Task requirements are ...
Sesh Commuri, V. Tadigotla, L. Sliger
ISCA
1994
IEEE
123views Hardware» more  ISCA 1994»
15 years 10 months ago
Software-Extended Coherent Shared Memory: Performance and Cost
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...
David Chaiken, Anant Agarwal
SAC
2005
ACM
16 years 4 days ago
A code compression advisory tool for embedded processors
We present a tool which is designed to be used as a code compression advisory system for object code to be run on an embedded processor. All the compression schemes support run-ti...
Sreejith K. Menon, Priti Shankar