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IPPS
2010
IEEE
15 years 4 months ago
Structuring the execution of OpenMP applications for multicore architectures
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
François Broquedis, Olivier Aumage, Brice G...
HICSS
2007
IEEE
141views Biometrics» more  HICSS 2007»
16 years 28 days ago
Second-Best Combinatorial Auctions - The Case of the Pricing-Per-Column Mechanism
One of the main contributions of classical mechanism design is the derivation of the Groves mechanisms. The class of Groves mechanisms are the only mechanisms that are strategy-pr...
Dirk Neumann, Björn Schnizler, Ilka Weber, Ch...
HPDC
2008
IEEE
15 years 6 months ago
Eliminating the middleman: peer-to-peer dataflow
Efficiently executing large-scale, data-intensive workflows such as Montage must take into account the volume and pattern of communication. When orchestrating data-centric workflo...
Adam Barker, Jon B. Weissman, Jano I. van Hemert
ISCA
2012
IEEE
270views Hardware» more  ISCA 2012»
13 years 9 months ago
Revisiting hardware-assisted page walks for virtualized systems
Recent improvements in architectural supports for virtualization have extended traditional hardware page walkers to traverse nested page tables. However, current twodimensional (2...
Jeongseob Ahn, Seongwook Jin, Jaehyuk Huh
DAC
2001
ACM
16 years 7 months ago
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems
Power-aware systems are those that must make the best use of available power. They subsume traditional low-power systems in that they must not only minimize power when the budget ...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi ...