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CAL
2008
15 years 6 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
RTAS
1997
IEEE
15 years 10 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
ICC
2007
IEEE
136views Communications» more  ICC 2007»
16 years 24 days ago
Combined Delay and Rate Differentiation Packet Scheduling for Multimedia Content Delivery in Satellite Broadcast/Multicast Syste
—The design of efficient packet scheduling algorithms is crucial to the radio resource management (RRM) in the satellite digital multimedia broadcasting (SDMB) system, which has ...
Hongfei Du, Linghang Fan, Barry G. Evans
IDA
2009
Springer
16 years 1 months ago
Selecting Computer Architectures by Means of Control-Flow-Graph Mining
Abstract Deciding which computer architecture provides the best performance for a certain program is an important problem in hardware design and benchmarking. While previous approa...
Frank Eichinger, Klemens Böhm
RTAS
1998
IEEE
15 years 10 months ago
Alleviating Priority Inversion and Non-Determinism in Real-Time CORBA ORB Core Architectures
There is increasing demand to extend Object Request Broker (ORB) middleware to support distributed applications with stringent real-time requirements. However, conventional ORB im...
Douglas C. Schmidt, Sumedh Mungee, Sergio Flores-G...