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FPL
2000
Springer
119views Hardware» more  FPL 2000»
15 years 10 months ago
A Self-Reconfigurable Gate Array Architecture
Abstract. This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chi...
Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro M...
NOMS
2000
IEEE
176views Communications» more  NOMS 2000»
15 years 10 months ago
Design and analysis of a proactive application management system (PAMS)
Management of large-scale Network-Centric Systems (NCS) and their applications is an extremely complex and challenging task due to factors such as centralized management architect...
Salim Hariri, Yoonhee Kim
DATE
2010
IEEE
160views Hardware» more  DATE 2010»
15 years 11 months ago
Soft error-aware design optimization of low power and time-constrained embedded systems
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu...
DAC
2002
ACM
16 years 7 months ago
IP delivery for FPGAs using Applets and JHDL
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
Michael J. Wirthlin, Brian McMurtrey
HPCA
2005
IEEE
16 years 6 months ago
Scatter-Add in Data Parallel Architectures
Many important applications exhibit large amounts of data parallelism, and modern computer systems are designed to take advantage of it. While much of the computation in the multi...
Jung Ho Ahn, Mattan Erez, William J. Dally