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MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
16 years 8 days ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
172
Voted
SIGMETRICS
2010
ACM
213views Hardware» more  SIGMETRICS 2010»
15 years 11 months ago
Small subset queries and bloom filters using ternary associative memories, with applications
Associative memories offer high levels of parallelism in matching a query against stored entries. We design and analyze an architecture which uses a single lookup into a Ternary C...
Ashish Goel, Pankaj Gupta
CF
2006
ACM
15 years 10 months ago
The potential of the cell processor for scientific computing
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As...
Samuel Williams, John Shalf, Leonid Oliker, Shoaib...
EUROSYS
2007
ACM
15 years 8 months ago
Enabling scalability and performance in a large scale CMP environment
Hardware trends suggest that large-scale CMP architectures, with tens to hundreds of processing cores on a single piece of silicon, are iminent within the next decade. While exist...
Bratin Saha, Ali-Reza Adl-Tabatabai, Anwar M. Ghul...
APIN
2006
136views more  APIN 2006»
15 years 6 months ago
Cell modeling with reusable agent-based formalisms
Biologists are building increasingly complex models and simulations of cells and other biological entities, and are looking at alternatives to traditional representations. Making ...
Ken Webb, Tony White