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DATE
2003
IEEE
151views Hardware» more  DATE 2003»
15 years 11 months ago
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
Adrijean Andriahantenaina, Hervé Charlery, ...
CODES
2004
IEEE
15 years 10 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
ICSM
1999
IEEE
15 years 10 months ago
A Two-Phase Process for Software Architecture Improvement
Software architecture is important for large systems in which it is the main means for, among other things, controlling complexity. Current ideas on software architectures were no...
René L. Krikhaar, André Postma, M. P...
ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
16 years 3 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik
CAISE
2004
Springer
15 years 12 months ago
Achieving Enterprise Model Interoperability through the Model-Based Architecture Framework for Enterprises
This paper describes an ontology for enterprise modelling, The ontology has enabled conceptual integration of two different modelling methodologies, one based on UEML (Unified Ente...
Håvard D. Jørgensen, Oddrun Pauline O...