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ICC
2007
IEEE
121views Communications» more  ICC 2007»
16 years 28 days ago
A QoS Architecture for IDMA-Based Multi-Service Wireless Networks
— The recent investigations on interleave-division multiple-access (IDMA) have demonstrated its advantage in supporting high-data-rate and multi-rate services over wireless fadin...
Qian Huang, Sammy Chan, King-Tim Ko, Li Ping, Peng...
IESS
2007
Springer
120views Hardware» more  IESS 2007»
16 years 22 days ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
ICPPW
2005
IEEE
16 years 5 days ago
Speculative Parallel Threading Architecture and Compilation
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
Xiao-Feng Li, Zhao-Hui Du, Chen Yang, Chu-Cheow Li...
TOMACS
1998
140views more  TOMACS 1998»
15 years 6 months ago
Technical Note: A Hierarchical Computer Architecture Design and Simulation Environment
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
Paul S. Coe, Fred W. Howell, Roland N. Ibbett, Lau...
CCS
2009
ACM
16 years 1 months ago
A practical property-based bootstrap architecture
Binary attestation, as proposed by the Trusted Computing Group (TCG), is a pragmatic approach for software integrity protection and verification. However, it has also various sho...
René Korthaus, Ahmad-Reza Sadeghi, Christia...