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CODES
2007
IEEE
16 years 1 months ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha
DAMON
2007
Springer
16 years 25 days ago
Architectural characterization of XQuery workloads on modern processors
As XQuery rapidly emerges as the standard for querying XML documents, it is very important to understand the architectural characteristics and behaviors of such workloads. A lot o...
Rubao Lee, Bihui Duan, Taoying Liu
TVLSI
2008
133views more  TVLSI 2008»
15 years 6 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
TNN
2010
185views Management» more  TNN 2010»
15 years 1 months ago
An adaptive multiobjective approach to evolving ART architectures
In this paper, we present the evolution of adaptive resonance theory (ART) neural network architectures (classifiers) using a multiobjective optimization approach. In particular, w...
Assem Kaylani, Michael Georgiopoulos, Mansooreh Mo...
IPPS
2003
IEEE
15 years 12 months ago
Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...