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MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
16 years 27 days ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
ECAI
1994
Springer
15 years 10 months ago
The DUAL Cognitive Architecture: A Hybrid Multi-Agent Approach
1 A hybrid (symbolic/connectionist) cognitive architecture, DUAL, is proposed. It is a multi-agent system which consist of a large number of non-cognitive, relatively simple agents...
Boicho N. Kokinov
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
15 years 6 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
TCSV
2002
119views more  TCSV 2002»
15 years 6 months ago
VLSI architecture design of MPEG-4 shape coding
This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 Video sta...
Hao-Chieh Chang, Yung-Chi Chang, Yi-Chu Wang, Wei-...
DAC
2007
ACM
16 years 7 months ago
Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors
Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultralow-power designs may even permit embedded systems...
Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert ...