39 search results - page 5 / 8 » Architectural Modifications to Enhance the Floating-Point Pe... |
161
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ERSA
2010
15 years 3 months ago
2010
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
134
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
121
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FPL
1995
Springer
15 years 9 months ago
1995
Springer
Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuumtube electronics [1], the increasing clock ...
185
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ISCC
2009
IEEE
16 years 20 days ago
2009
IEEE
—This paper presents a reconfigurable architecture for the session initiation protocol (SIP). SIP is a protocol used primarily to establish point-to-point sessions between users...
133
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FPL
2007
Springer
16 years 3 days ago
2007
Springer
Programmable logic cores (PLCs) offer a means of providing post-fabrication re-configurability to a SoC design. Circuits implemented in a PLC will inevitably have lower timing per...