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CODES
2006
IEEE
16 years 13 days ago
A bus architecture for crosstalk elimination in high performance processor design
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increas...
Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
WIKIS
2010
ACM
15 years 6 months ago
ThinkFree: using a visual Wiki for IT knowledge management in a tertiary institution
We describe ThinkFree, an industrial Visual Wiki application which provides a way for end users to better explore knowledge of IT Enterprise Architecture assets that is held withi...
Christian Hirsch, John G. Hosking, John C. Grundy,...
PPL
2008
185views more  PPL 2008»
15 years 6 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
ISVLSI
2006
IEEE
149views VLSI» more  ISVLSI 2006»
16 years 12 days ago
Defect-Aware Design Paradigm for Reconfigurable Architectures
With advances in process technology, the feature sizes are decreasing, which leads to higher defect densities. More sophisticated techniques, at increased costs are required to av...
Rahul Jain, Anindita Mukherjee, Kolin Paul
DATE
2005
IEEE
108views Hardware» more  DATE 2005»
16 years 5 hour ago
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik