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» Architectural Considerations with Distributed Computing
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HPCA
2005
IEEE
16 years 6 months ago
A Small, Fast and Low-Power Register File by Bit-Partitioning
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
Masaaki Kondo, Hiroshi Nakamura
HPCA
2005
IEEE
16 years 6 months ago
SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs
Memory leaks and memory corruption are two major forms of software bugs that severely threaten system availability and security. According to the US-CERT Vulnerability Notes Datab...
Feng Qin, Shan Lu, Yuanyuan Zhou
HPCA
2005
IEEE
16 years 6 months ago
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
In this paper, we study the instruction cache miss behavior of four modern commercial applications (a database workload, TPC-W, SPECjAppServer2002 and SPECweb99). These applicatio...
Lawrence Spracklen, Yuan Chou, Santosh G. Abraham
HPCA
2005
IEEE
16 years 6 months ago
Characterizing and Comparing Prevailing Simulation Techniques
Due to the simulation time of the reference input set, architects often use alternative simulation techniques. Although these alternatives reduce the simulation time, what has not...
Joshua J. Yi, Sreekumar V. Kodakara, Resit Sendag,...
HPCA
2005
IEEE
16 years 6 months ago
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors
Memory system optimizations have been well studied on single-threaded systems; however, the wide use of simultaneous multithreading (SMT) techniques raises questions over their ef...
Zhichun Zhu, Zhao Zhang