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140
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VLSID
2008
IEEE
16 years 6 months ago
2008
IEEE
In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long cha...
164
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VLSID
2005
IEEE
16 years 6 months ago
2005
IEEE
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
140
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VLSID
2005
IEEE
16 years 6 months ago
2005
IEEE
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
171
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VLSID
2003
IEEE
16 years 6 months ago
2003
IEEE
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
169
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VLSID
2001
IEEE
16 years 6 months ago
2001
IEEE
A technique for signature based diagnosis using windows of different sizes is presented. It allows to obtain increased diagnostic information from a given test at a lower cost, wi...