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178
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ICS
1999
Tsinghua U.
15 years 10 months ago
1999
Tsinghua U.
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
181
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ICPADS
1998
IEEE
15 years 10 months ago
1998
IEEE
This paper describes a scalable Web server array architecture which uses a caching policy called Probability Based Replacement (PBR) algorithm [5, 6]. The server array consists of...
194
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ICPP
1998
IEEE
15 years 10 months ago
1998
IEEE
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
174
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IPPS
1998
IEEE
15 years 10 months ago
1998
IEEE
In this paper, the effect of switch design on the application performance of cache-coherent non-uniform memory access (CC-NUMA) multiprocessors is studied in detail. Wormhole rout...
165
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IPPS
1998
IEEE
15 years 10 months ago
1998
IEEE
Instruction scheduling methods based on the construction of state diagrams (or automata) have been used for architectures involving deeply pipelined function units. However, the s...