This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
This paper studies a way to improve consistency of states in a ball game typed DVE with lag, in P2P architecture. We also study how to control shared objects in real-time in a ser...
Leakage current has become a stringent constraint in today’s processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inver...
Rajeev R. Rao, Anirudh Devgan, David Blaauw, Denni...
A new scalable optical network infrastructure SMART is proposed based on light-trails and hypernetwork architecture. The underlying physical network of SMART is a reconfigurable WD...
Random test generators are often used to create regression suites on-the-fly. Regression suites are commonly generated by choosing several specifications and generating a number o...