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159
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IPPS
2006
IEEE
16 years 19 days ago
2006
IEEE
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
164
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PDCAT
2004
Springer
15 years 12 months ago
2004
Springer
Abstract. This paper proposes a simplified simultaneous multithreading (SMT) architecture aiming at CPU cores of embedded SoCs for consumer applications. This architecture reduces...
153
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IPPS
2009
IEEE
16 years 1 months ago
2009
IEEE
We consider two flow control schemes for Best Effort traffic in on-chip architectures, which can be deemed as the solutions to the boundary extremes of a class of utility maximi...
181
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IPPS
2007
IEEE
16 years 27 days ago
2007
IEEE
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
200
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IPPS
2006
IEEE
16 years 19 days ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...