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FPGA
1999
ACM
155views FPGA» more  FPGA 1999»
15 years 10 months ago
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density
In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transist...
Vaughn Betz, Jonathan Rose
SRDS
2007
IEEE
16 years 17 days ago
The Fail-Heterogeneous Architectural Model
Fault tolerant distributed protocols typically utilize a homogeneous fault model, either fail-crash or fail-Byzantine, where all processors are assumed to fail in the same manner....
Marco Serafini, Neeraj Suri
DATE
2005
IEEE
134views Hardware» more  DATE 2005»
15 years 12 months ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
HPDC
2005
IEEE
15 years 12 months ago
Genetic algorithm based automatic data partitioning scheme for HPF
good data partitioning scheme is the need of the time. However it is very diflcult to arrive at a good solution as the number of possible dutupartitionsfor a given real lifeprogra...
Sunil Kumar Anand, Y. N. Srikant