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DSD
2007
IEEE
160views Hardware» more  DSD 2007»
16 years 1 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
SAMOS
2004
Springer
16 years 2 days ago
High-Level Energy Estimation for ARM-Based SOCs
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
ADHOC
2007
102views more  ADHOC 2007»
15 years 6 months ago
On the capacity of the single source multiple relay single destination mesh network
In this paper, we derive the information theoretic capacity of a special class of mesh networks. A mesh network is a heterogeneous wireless network in which the transmission among...
Lawrence Ong, Mehul Motani
COMCOM
2007
168views more  COMCOM 2007»
15 years 6 months ago
An efficient cluster-based multi-channel management protocol for wireless Ad Hoc networks
—In Ad Hoc networking, cluster-based communication protocol can reduce large amount of flooding packets in route establishment process. However, the 802.11 medium access control ...
Gwo-Jong Yu, Chih-Yung Chang
HOTI
2011
IEEE
14 years 6 months ago
iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture
Abstract—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power cons...
Dominic DiTomaso, Avinash Kodi, Savas Kaya, David ...