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TVLSI
2010
15 years 1 months ago
SRAM Read/Write Margin Enhancements Using FinFETs
Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve ...
Andrew Carlson, Zheng Guo, Sriram Balasubramanian,...
TVLSI
2010
15 years 1 months ago
A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization
Hardware debuggers and logic analyzers must be able to record a continuous trace of data. Since the trace data are tremendous, to save space, these traces are often compressed. The...
Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang
TVLSI
2010
15 years 1 months ago
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
Rupak Samanta, Jiang Hu, Peng Li
TWC
2010
15 years 1 months ago
Rateless coding for hybrid free-space optical and radio-frequency communication
Abstract--Free-space optical (FSO) transmission systems enable high-speed communication with relatively small deployment costs. However, FSO suffers a critical disadvantage, namely...
Ali AbdulHussein, Anand Oka, Trung Thanh Nguyen 00...
TWC
2010
15 years 1 months ago
Performance of asynchronous two-relay two-hop wireless cooperative networks
In wireless cooperative networks, the asynchronism between the relays can be a source of diversity which is similar in its essence to the multipath diversity of frequency selectiv...
Michel Nahas, Ahmed Saadani, Walid Hachem
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