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DATE
2003
IEEE
91views Hardware» more  DATE 2003»
15 years 12 months ago
Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs
In system-level platform-based embedded systems design, the mapping model is a crucial link between the application model and the architecture model. All three models must match w...
Vladimir D. Zivkovic, Erwin A. de Kock, Pieter van...
DATE
2009
IEEE
107views Hardware» more  DATE 2009»
16 years 1 months ago
User-centric design space exploration for heterogeneous Network-on-Chip platforms
- In this paper, we present a design methodology for automatic platform generation of future heterogeneous systems where communication happens via the Network-onChip (NoC) approach...
Chen-Ling Chou, Radu Marculescu
VLSISP
2010
148views more  VLSISP 2010»
15 years 5 months ago
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunso...
ARC
2010
Springer
183views Hardware» more  ARC 2010»
15 years 6 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
SBCCI
2005
ACM
115views VLSI» more  SBCCI 2005»
16 years 6 days ago
Design of a decompressor engine on a SPARC processor
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
Richard E. Billo, Rodolfo Azevedo, Guido Araujo, P...