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AGTIVE
2007
Springer
15 years 10 months ago
Transforming Timeline Specifications into Automata for Runtime Monitoring
Abstract. In runtime monitoring, a programmer specifies code to execute whenever a sequence of events occurs during program execution. Previous and related work has shown that runt...
Eric Bodden, Hans Vangheluwe
SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
16 years 7 hour ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
CODES
2007
IEEE
15 years 10 months ago
A computational reflection mechanism to support platform debugging in SystemC
System-level and Platform-based design, along with Transaction Level modeling (TLM) techniques and languages like SystemC, appeared as a response to the ever increasing complexity...
Bruno Albertini, Sandro Rigo, Guido Araujo, Cristi...
ECAI
2008
Springer
15 years 8 months ago
Temporal Logic Patterns for Querying Qualitative Models of Genetic Regulatory Networks
Formal verification based on model checking provides a powerful technology to query qualitative models of dynamical systems. The application of model-checking approaches is hamper...
Pedro T. Monteiro, Delphine Ropers, Radu Mateescu,...
NFM
2011
306views Formal Methods» more  NFM 2011»
15 years 1 months ago
Generalized Rabin(1) Synthesis with Applications to Robust System Synthesis
Synthesis of finite-state machines from linear-time temporal logic (LTL) formulas is an important formal specification debugging technique for reactive systems and can quickly ge...
Rüdiger Ehlers