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ISPASS
2006
IEEE
16 years 16 days ago
Automatic testcase synthesis and performance model validation for high performance PowerPC processors
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John,...
ICPPW
2005
IEEE
16 years 4 days ago
Speculative Parallel Threading Architecture and Compilation
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
Xiao-Feng Li, Zhao-Hui Du, Chen Yang, Chu-Cheow Li...
WMASH
2004
ACM
15 years 12 months ago
Secure universal mobility for wireless internet
The advent of the mobile wireless Internet has created the need for seamless and secure communication over heterogeneous access networks such as IEEE 802.11, WCDMA, cdma2000, and ...
Ashutosh Dutta, Tao Zhang, Sunil Madhani, Kenichi ...
OOPSLA
2004
Springer
15 years 12 months ago
Method-level phase behavior in java workloads
Java workloads are becoming more and more prominent on various computing devices. Understanding the behavior of a Java workload which includes the interaction between the applicat...
Andy Georges, Dries Buytaert, Lieven Eeckhout, Koe...
RSP
2000
IEEE
156views Control Systems» more  RSP 2000»
15 years 11 months ago
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya