1398 search results - page 215 / 280 » Application-Specific Integrated Circuits |
147
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GLVLSI
2010
IEEE
15 years 11 months ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
176
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GLVLSI
1998
IEEE
15 years 10 months ago
1998
IEEE
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally u...
169
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ISPD
1997
ACM
15 years 10 months ago
1997
ACM
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...
157
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
This paper presents a novel placement algorithm for timing optimization based on a new and powerful concept, which we term differential timing analysis. Recognizing that accurate ...
164
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DAC
2010
ACM
15 years 7 months ago
2010
ACM
This work proposes a new problem of identifying large and tangled logic structures in a synthesized netlist. Large groups of cells that are highly interconnected to each other can...