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IPPS
2007
IEEE
16 years 26 days ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
SRDS
2008
IEEE
16 years 28 days ago
An Incremental File System Consistency Checker for Block-Level CDP Systems
A block-level continuous data protection (CDP) system logs every disk block update from an application server (e.g., a file or DBMS server) to a storage system so that any disk u...
Maohua Lu, Tzi-cker Chiueh, Shibiao Lin
ISCAS
2006
IEEE
124views Hardware» more  ISCAS 2006»
16 years 17 days ago
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4
Abstract— There is a clear trend of future embedded systems in moving toward wireless, multimedia, multi-functional and ubiquitous applications. This emerges new challenges in th...
Alexandros Bartzas, Miguel Peón Quiró...
OSDI
1994
ACM
15 years 7 months ago
Scheduling for Reduced CPU Energy
The energy usage of computer systems is becoming more important, especially for battery operated systems. Displays, disks, and cpus, in that order, use the most energy. Reducing t...
Mark Weiser, Brent B. Welch, Alan J. Demers, Scott...
STOC
2006
ACM
121views Algorithms» more  STOC 2006»
16 years 15 days ago
On adequate performance measures for paging
Memory management is a fundamental problem in computer architecture and operating systems. We consider a two-level memory system with fast, but small cache and slow, but large mai...
Konstantinos Panagiotou, Alexander Souza