3171 search results - page 227 / 635 » Application of Reduce Order Modeling to Time Parallelization |
142
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TC
2008
15 years 6 months ago
2008
Component failures and planned component replacements cause changes in the topology and routing paths supplied by the interconnection network of a parallel processor system over ti...
175
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EUROPAR
2009
Springer
15 years 11 months ago
2009
Springer
This paper addresses the issue of how to meet the strict timing constraints of (soft) real-time virtualized applications while the Virtual Machine (VM) hosting them is undergoing a...
166
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GECCO
2006
Springer
15 years 10 months ago
2006
Springer
Garbage collection can be a performance bottleneck in large distributed, multi-threaded applications. Applications may produce millions of objects during their lifetimes and may i...
169
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BCS
2008
15 years 8 months ago
2008
This paper describes a customisable processor designed to accelerate execution of inductive logic programming, targeting advanced field-programmable gate array (FPGA) technology. ...
176
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ASIACRYPT
2009
Springer
16 years 1 months ago
2009
Springer
We demonstrate how the framework that is used for creating efficient number-theoretic ID and signature schemes can be transferred into the setting of lattices. This results in cons...