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» Application of Reduce Order Modeling to Time Parallelization
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TVLSI
2010
15 years 1 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
VLDB
1994
ACM
137views Database» more  VLDB 1994»
15 years 10 months ago
Performance of Data-Parallel Spatial Operations
The performance of data-parallel algorithms for spatial operations using data-parallel variants of the bucket PMR quadtree, R-tree, and R+-tree spatial data structures is compared...
Erik G. Hoel, Hanan Samet
SIGPLAN
2008
15 years 6 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
SI3D
2010
ACM
16 years 1 months ago
Parallel Banding Algorithm to compute exact distance transform with the GPU
We propose a Parallel Banding Algorithm (PBA) on the GPU to compute the exact Euclidean Distance Transform (EDT) for a binary image in 2D and higher dimensions. Partitioning the i...
Thanh-Tung Cao, Ke Tang, Anis Mohamed, Tiow Seng T...
NIPS
2008
15 years 8 months ago
Scalable Algorithms for String Kernels with Inexact Matching
We present a new family of linear time algorithms based on sufficient statistics for string comparison with mismatches under the string kernels framework. Our algorithms improve t...
Pavel P. Kuksa, Pai-Hsi Huang, Vladimir Pavlovic