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» Application of Reduce Order Modeling to Time Parallelization
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LCPC
2009
Springer
15 years 11 months ago
A Communication Framework for Fault-Tolerant Parallel Execution
PC grids represent massive computation capacity at a low cost, but are challenging to employ for parallel computing because of variable and unpredictable performance and availabili...
Nagarajan Kanna, Jaspal Subhlok, Edgar Gabriel, Es...
CCGRID
2006
IEEE
16 years 17 days ago
Statistical Properties of Task Running Times in a Global-Scale Grid Environment
— Over the years, the use of global grid environments have become widespread. In order to make applications robust against the dynamics of those grid environments it is essential...
Menno Dobber, Robert D. van der Mei, Ger Koole
IPPS
2000
IEEE
15 years 11 months ago
Three Dimensional VLSI-Scale Interconnects
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processo...
Dennis W. Prather
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
16 years 1 months ago
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform
— Multiprocessors on a chip are the reality of these days. Semiconductor industry has recognized this approach as the most efficient in order to exploit chip resources, but the ...
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Ma...
HPCA
2011
IEEE
14 years 10 months ago
Beyond block I/O: Rethinking traditional storage primitives
Over the last twenty years the interfaces for accessing persistent storage within a computer system have remained essentially unchanged. Simply put, seek, read and write have de...
Xiangyong Ouyang, David W. Nellans, Robert Wipfel,...