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161
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ICS
2009
Tsinghua U.
16 years 1 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
161
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HPCA
2006
IEEE
16 years 6 months ago
2006
IEEE
Processor architects have a challenging task of evaluating a large design space consisting of several interacting parameters and optimizations. In order to assist architects in ma...
142
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SIGMETRICS
1990
ACM
15 years 10 months ago
1990
ACM
Recently we presented several disk array architectures designed to increase the data rate and I/O rate of supercomputing applications, transaction processing, and file systems [Pat...
157
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WSC
2007
15 years 8 months ago
2007
Event simulation and analytic modeling are used to evaluate the performance of Low Latency Queueing (LLQ), a queueing discipline available in some Internet packet switching router...
188
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MICCAI
2003
Springer
16 years 7 months ago
2003
Springer
Abstract. When developing statistical models of normal brain perfusion, two questions are of crucial interest: How well does an atlas describe normality and how sensitive is it at ...