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DAC
1999
ACM
15 years 11 months ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung
ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
15 years 11 months ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah
ISPD
1999
ACM
98views Hardware» more  ISPD 1999»
15 years 11 months ago
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable cha...
Dirk Stroobandt, Peter Verplaetse, Jan Van Campenh...
ICCAD
1999
IEEE
113views Hardware» more  ICCAD 1999»
15 years 11 months ago
Attractor-repeller approach for global placement
Traditionally, analytic placement used linear or quadratic wirelength objective functions. Minimizing either formulation attracts cells sharing common signals (nets) together. The...
Hussein Etawil, Shawki Areibi, Anthony Vannelli
ICCAD
1999
IEEE
120views Hardware» more  ICCAD 1999»
15 years 11 months ago
Regularity extraction via clan-based structural circuit decomposition
Identifying repeating structural regularities in circuits allows the minimization of synthesis, optimization, and layout e orts. We introduce in this paper a novel method for ident...
Soha Hassoun, Carolyn McCreary
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