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GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
15 years 11 months ago
CMOS system-on-a-chip voltage scaling beyond 50nm
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoo...
HPCA
2000
IEEE
15 years 11 months ago
Improving the Throughput of Synchronization by Insertion of Delays
Efficiency of synchronization mechanisms can limit the parallel performance of many shared-memory applications. In addition, the ever increasing performance gap between processor...
Ravi Rajwar, Alain Kägi, James R. Goodman
HPCA
2000
IEEE
15 years 11 months ago
Register Organization for Media Processing
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...
Scott Rixner, William J. Dally, Brucek Khailany, P...
ICCD
2000
IEEE
159views Hardware» more  ICCD 2000»
15 years 11 months ago
Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures
This paper aims to provide a quantitative understanding of the performance of DSP and multimedia applications on very long instruction word (VLIW), single instruction multiple dat...
Deependra Talla, Lizy Kurian John, Viktor S. Lapin...
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
15 years 11 months ago
Memory access scheduling
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
Scott Rixner, William J. Dally, Ujval J. Kapasi, P...
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