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SIGARCH
2008
97views more  SIGARCH 2008»
15 years 6 months ago
SP-NUCA: a cost effective dynamic non-uniform cache architecture
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
Javier Merino, Valentin Puente, Pablo Prieto, Jos&...
TCSV
2008
225views more  TCSV 2008»
15 years 6 months ago
Analysis and Efficient Architecture Design for VC-1 Overlap Smoothing and In-Loop Deblocking Filter
Abstract--In contrast to the macroblock-based in-loop deblocking filters, the filters of VC-1 perform all horizontal edges (for in-loop filtering) or vertical edges (for overlap sm...
Yen-Lin Lee, T. Q. Nguyen
IEEEMM
2002
134views more  IEEEMM 2002»
15 years 6 months ago
A Middleware Architecture for Open and Interoperable GISs
an abstract model for information sharing and integration and use it to develop an architecture for building open, component-based, interoperable systems. A geographic information ...
Steven H. Wong, Steven L. Swartz, Dilip Sarkar
SIGOPS
2011
255views Hardware» more  SIGOPS 2011»
15 years 1 months ago
Bridging functional heterogeneity in multicore architectures
Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single– threaded performance coupled with high multi–threaded through...
Dheeraj Reddy, David A. Koufaty, Paul Brett, Scott...
HPCA
2006
IEEE
16 years 7 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...