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DAC
2001
ACM
16 years 7 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...
IPPS
2007
IEEE
16 years 1 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
MONET
2010
125views more  MONET 2010»
15 years 5 months ago
GTPP: General Truncated Pyramid Peer-to-Peer Architecture over Structured DHT Networks
— Hierarchical Distributed Hash Table (DHT) architectures have been among the most interesting research topics since the birth of flat DHT architecture. However, most of the prev...
Zhonghong Ou, Erkki Harjula, Timo Koskela, Mika Yl...
JSS
2010
120views more  JSS 2010»
15 years 1 months ago
Handling communications in process algebraic architectural description languages: Modeling, verification, and implementation
Architectural description languages are a useful tool for modeling complex systems at a high level of abstraction. If based on formal methods, they can also serve for enabling the...
Marco Bernardo, Edoardo Bontà, Alessandro A...
HPCN
2000
Springer
15 years 10 months ago
An Analytical Model for a Class of Architectures under Master-Slave Paradigm
We build an analytical model for an application utilizing master-slave paradigm. In the model, only three architecture parameters are used: latency, bandwidth and flop rate. Instea...
Yasemin Yalçinkaya, Trond Steihaug