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IBMRD
2006
76views more  IBMRD 2006»
15 years 6 months ago
Modeling wire delay, area, power, and performance in a simulation infrastructure
We present Justice, a set of extensions to the Liberty simulation infrastructure that model area, wire length, and power consumption in processor architectures. Given an architectu...
Nicholas P. Carter, Azmat Hussain
ICCD
2008
IEEE
175views Hardware» more  ICCD 2008»
16 years 3 months ago
Contention-aware application mapping for Network-on-Chip communication architectures
- In this paper, we analyze the impact of network contention on the application mapping for tile-based Networkon-Chip (NoC) architectures. Our main theoretical contribution consist...
Chen-Ling Chou, Radu Marculescu
ICCD
2007
IEEE
190views Hardware» more  ICCD 2007»
16 years 3 months ago
Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits
Hybrid nanoelectronics are emerging as one viable option to sustain the Moore’s Law after the CMOS scaling limit is reached. One main design challenge in hybrid nanoelectronics ...
Shu Li, Tong Zhang
COMPSAC
2008
IEEE
16 years 1 months ago
An Adaptive Software Architecture Model Based on Component-Mismatches Detection and Elimination
Commercial-off-the-shelf components (COTS) are widely reused at present and black-box composition is the unique way to integrate them into the target system. However, various mism...
Shan Tang, Xin Peng, Yiming Lau, Wenyun Zhao, Zhix...
IPPS
2006
IEEE
16 years 21 days ago
Timed automata based analysis of embedded system architectures
We show that timed automata can be used to model and to analyze timeliness properties of embedded system architectures. Using a case study inspired by industrial practice, we pres...
Martijn Hendriks, Marcel Verhoef