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DATE
2007
IEEE
85views Hardware» more  DATE 2007»
16 years 1 months ago
Timing simulation of interconnected AUTOSAR software-components
AUTOSAR is a recent specification initiative which focuses on a model-driven architecture like methodology for automotive applications. However, needed engineering steps, or how-t...
Matthias Krause, Oliver Bringmann, André He...
FPL
2007
Springer
120views Hardware» more  FPL 2007»
16 years 25 days ago
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays
In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameter...
Yohei Hasegawa, Hideharu Amano
DATE
2003
IEEE
151views Hardware» more  DATE 2003»
15 years 12 months ago
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
Adrijean Andriahantenaina, Hervé Charlery, ...
IWCMC
2009
ACM
15 years 11 months ago
Interference and throughput analyses in dual-polarized wireless networks subject to Rayleigh fading
This paper investigates the impact of the polarization on the achievable throughput and the probability of successful transmission in the cellular network architectures. A channel...
Jean-Michel Dricot, François Horlin, Philip...
DAC
1997
ACM
15 years 11 months ago
A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...
Claus Schneider