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HPCA
2006
IEEE
16 years 7 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
HIPEAC
2009
Springer
16 years 1 months ago
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
Michael B. Henry, Leyla Nazhandali
ICPP
2007
IEEE
16 years 29 days ago
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management
As the number of computing and storage nodes keeps increasing, the interconnection network is becoming a key element of many computing and communication systems, where the overall...
Gaspar Mora, Pedro Javier García, Jose Flic...
CGO
2006
IEEE
16 years 22 days ago
A Cross-Architectural Interface for Code Cache Manipulation
Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentiallyaltered copy of ever...
Kim M. Hazelwood, Robert S. Cohn
IISWC
2006
IEEE
16 years 21 days ago
Performance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 Architecture
— As x86-64 processors become the CPU of choice for the personal computer market, it becomes increasingly important to understand the performance we can expect by migrating appli...
Dong Ye, Joydeep Ray, Christophe Harle, David R. K...