: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
This paper presents the Architecture Tradeoff Analysis Method (ATAM), a structured technique for understanding the tradeoffs inherent in design. This method was developed to provi...
Rick Kazman, Mark H. Klein, Mario Barbacci, Thomas...
— Hierarchical Distributed Hash Table (DHT) architectures have been among the most interesting research topics since the birth of flat DHT architecture. However, most of the prev...
Zhonghong Ou, Erkki Harjula, Timo Koskela, Mika Yl...