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JUCS
2000
120views more  JUCS 2000»
15 years 6 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
DAC
2001
ACM
16 years 7 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...
IPPS
2007
IEEE
16 years 29 days ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
ICECCS
1998
IEEE
168views Hardware» more  ICECCS 1998»
15 years 11 months ago
The Architecture Tradeoff Analysis Method
This paper presents the Architecture Tradeoff Analysis Method (ATAM), a structured technique for understanding the tradeoffs inherent in design. This method was developed to provi...
Rick Kazman, Mark H. Klein, Mario Barbacci, Thomas...
MONET
2010
125views more  MONET 2010»
15 years 5 months ago
GTPP: General Truncated Pyramid Peer-to-Peer Architecture over Structured DHT Networks
— Hierarchical Distributed Hash Table (DHT) architectures have been among the most interesting research topics since the birth of flat DHT architecture. However, most of the prev...
Zhonghong Ou, Erkki Harjula, Timo Koskela, Mika Yl...