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DAC
2008
ACM
16 years 7 months ago
On the role of timing masking in reliable logic circuit design
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
DAC
2001
ACM
16 years 7 months ago
Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation
In this paper, we present a new technique for the e cient dynamic detection and removal of inactive clauses, i.e. clauses that do not a ect the solutions of interest of a Boolean ...
Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav A...
DAC
2002
ACM
16 years 7 months ago
HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery
This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we devel...
Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Ch...
DAC
2003
ACM
16 years 7 months ago
Multilevel global placement with retiming
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
Jason Cong, Xin Yuan
DAC
2003
ACM
16 years 7 months ago
Coverage directed test generation for functional verification using bayesian networks
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
Shai Fine, Avi Ziv
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