Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
In this paper, we present a new technique for the e cient dynamic detection and removal of inactive clauses, i.e. clauses that do not a ect the solutions of interest of a Boolean ...
This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we devel...
Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Ch...
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...