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DAC
2007
ACM
16 years 7 months ago
Modeling the Function Cache for Worst-Case Execution Time Analysis
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
Raimund Kirner, Martin Schoeberl
ISIM
2007
15 years 8 months ago
Verification of Good Design Style of UML Models
Software architecture, and its behavior can be expressed as UML models. Models of complex systems can be also complex and hard to read – they may consists of hundreds of artifact...
Bogumila Hnatkowska
DAC
2010
ACM
15 years 10 months ago
Towards scalable system-level reliability analysis
State-of-the-art automatic reliability analyses as used in system-level design approaches mainly rely on Binary Decision Diagrams (BDDs) and, thus, face two serious problems: (1) ...
Michael Glaß, Martin Lukasiewycz, Christian ...
CODES
2006
IEEE
15 years 10 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
VLSID
2008
IEEE
191views VLSI» more  VLSID 2008»
16 years 26 days ago
Programming and Performance Modelling of Automotive ECU Networks
The last decade has seen a phenomenal increase in the use of electronic components in automotive systems, resulting in the replacement of purely mechanical or hydraulic-implementa...
Samarjit Chakraborty, Sethu Ramesh