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DAC
2006
ACM
16 years 7 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
CASES
2006
ACM
16 years 15 days ago
FlashCache: a NAND flash memory file cache for low power web servers
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
Taeho Kgil, Trevor N. Mudge
MTV
2003
IEEE
109views Hardware» more  MTV 2003»
15 years 11 months ago
A Methodology for Validation of Microprocessors using Equivalence Checking
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Nikil D. Dutt
WICSA
2004
15 years 8 months ago
Understanding Tradeoffs among Different Architectural Modeling Approaches
Over the past decade a number of architecture description languages (ADLs) have been proposed to facilitate modeling and analysis of software architecture. While each claims to ha...
Roshanak Roshandel, Bradley R. Schmerl, Nenad Medv...
ISSS
1998
IEEE
120views Hardware» more  ISSS 1998»
15 years 10 months ago
Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
Ing-Jer Huang, Ping-Huei Xie