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DAC
2003
ACM
16 years 7 months ago
A retargetable micro-architecture simulator
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
Wai Sum Mong, Jianwen Zhu
VLSID
2009
IEEE
177views VLSI» more  VLSID 2009»
16 years 7 months ago
Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study
Many system-level design tasks (e.g. timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-ha...
Unmesh D. Bordoloi, Samarjit Chakraborty
DAC
2011
ACM
14 years 6 months ago
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation te...
Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhr...
FDL
2007
IEEE
16 years 25 days ago
Time Modeling in MARTE
This article introduces the Time Model subprofile of MARTE, a new OMG UML Profile dedicated to Modeling and Analysis of Real-Time and Embedded systems. After a brief presentatio...
Robert de Simone, Charles André
EUROMICRO
2007
IEEE
16 years 25 days ago
Using Model Differencing for Architecture-level Regression Testing
Regression testing can be systematically applied at the software architecture level in order to reduce the cost of retesting modified systems, and also to assess the regression t...
Henry Muccini