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DATE
2003
IEEE
151views Hardware» more  DATE 2003»
15 years 11 months ago
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
Adrijean Andriahantenaina, Hervé Charlery, ...
IPPS
2008
IEEE
16 years 27 days ago
Translational research design templates, Grid computing, and HPC
Design templates that involve discovery, analysis, and integration of information resources commonly occur in many scientific research projects. In this paper we present examples o...
Joel H. Saltz, Scott Oster, Shannon Hastings, Step...
SAC
2009
ACM
16 years 1 months ago
Development of a biosignals framework for usability analysis
The understanding of human physical and physiological signals and expressions, together with a growing processing and control capacity allows for new approaches in interactive sys...
Inês Oliveira, Rui Lopes, Nuno Guimarã...
ECBS
2003
IEEE
84views Hardware» more  ECBS 2003»
15 years 11 months ago
Model-Integrated Design Toolset for Polymorphous Computer-Based Systems
Polymorphous computer-based systems are systems in which the CPU architecture “morphs” or changes shape to meet the requirements of the application. Optimized and efficient de...
Brandon Eames, Ted Bapty, Ben Abbott, Sandeep Neem...
ESTIMEDIA
2006
Springer
15 years 10 months ago
A Mixed-level Co-simulation Method for System-level Design Space Exploration
The Sesame modeling and simulation framework aims at efficient system-level design space exploration of embedded multimedia systems. A primary objective of Sesame is the ion at mu...
Mark Thompson, Andy D. Pimentel, Simon Polstra, Ca...