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» Analysis of Design Process Dynamics
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DFT
2009
IEEE
189views VLSI» more  DFT 2009»
16 years 1 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
HICSS
2003
IEEE
127views Biometrics» more  HICSS 2003»
16 years 9 days ago
Storage Model for CDA Documents
The Health Level 7 Clinic Document Architecture (CDA) is an XML-based document markup standard that specifies the hierarchical structure and semantics of “clinical documents” ...
Zheng Liang, Peter Bodorik, Michael Shepher
DAC
2007
ACM
16 years 8 months ago
The Case for Low-Power Photonic Networks on Chip
Packet-switched networks on chip (NoC) have been advocated as a natural communication mechanism among the processing cores in future chip multiprocessors (CMP). However, electroni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
DAC
2007
ACM
16 years 8 months ago
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift
Statistical behavior of device leakage and threshold voltage shows a strong width dependency under microscopic random dopant fluctuation. Leakage estimation using the conventional...
Jie Gu, Sachin S. Sapatnekar, Chris H. Kim
PDC
2004
ACM
16 years 13 days ago
Ways of grounding imagination
This paper discusses and evaluates use of different participatory design methods in relation to addressing the challenge of grounding imagination. It presents reflections on the u...
Monika Büscher, Mette Agger Eriksen, Jannie F...