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DAC
2002
ACM
16 years 7 months ago
Scheduler-based DRAM energy management
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...
Victor Delaluz, Anand Sivasubramaniam, Mahmut T. K...
DSD
2009
IEEE
144views Hardware» more  DSD 2009»
16 years 1 months ago
Composable Resource Sharing Based on Latency-Rate Servers
Abstract—Verification of application requirements is becoming a bottleneck in system-on-chip design, as the number of applications grows. Traditionally, the verification comple...
Benny Akesson, Andreas Hansson, Kees Goossens
JSSPP
2004
Springer
16 years 4 days ago
Performance Implications of Failures in Large-Scale Cluster Scheduling
As we continue to evolve into large-scale parallel systems, many of them employing hundreds of computing engines to take on mission-critical roles, it is crucial to design those s...
Yanyong Zhang, Mark S. Squillante, Anand Sivasubra...
BMCBI
2006
179views more  BMCBI 2006»
15 years 6 months ago
Multiscale Hy3S: Hybrid stochastic simulation for supercomputers
Background: Stochastic simulation has become a useful tool to both study natural biological systems and design new synthetic ones. By capturing the intrinsic molecular fluctuation...
Howard Salis, Vassilios Sotiropoulos, Yiannis N. K...
ISLPED
2007
ACM
169views Hardware» more  ISLPED 2007»
15 years 8 months ago
Throughput of multi-core processors under thermal constraints
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...