192 search results - page 36 / 39 » Analysis and Prediction of Performance for Evolving Architec... |
195
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BMCBI
2007
15 years 6 months ago
2007
Background: This work explores the quantitative characteristics of the local transcriptional regulatory network based on the availability of time dependent gene expression data se...
154
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DSD
2009
IEEE
16 years 24 days ago
2009
IEEE
Abstract—Verification of application requirements is becoming a bottleneck in system-on-chip design, as the number of applications grows. Traditionally, the verification comple...
180
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CODES
2005
IEEE
15 years 11 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
141
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SIGCOMM
2004
ACM
15 years 11 months ago
2004
ACM
−Buffered multistage interconnection networks offer one of the most scalable and cost-effective approaches to building high capacity routers. Unfortunately, the performance of su...
215
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SIGCOMM
2005
ACM
15 years 11 months ago
2005
ACM
Hash table is used as one of the fundamental modules in several network processing algorithms and applications such as route lookup, packet classification, per-flow state manage...