3120 search results - page 98 / 624 » An optimal architecture for a DDC |
221
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CCS
2011
ACM
14 years 6 months ago
2011
ACM
Network intrusion detection systems are faced with the challenge of identifying diverse attacks, in extremely high speed networks. For this reason, they must operate at multi-Giga...
211
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ISCAPDCS
2004
15 years 7 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
162
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CN
2002
15 years 6 months ago
2002
We describe the design, implementation and performance of a high-performance Web server accelerator which runs on an embedded operating system and improves Web server performance ...
208
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ISCA
2012
IEEE
13 years 8 months ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
184
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ICCAD
2002
IEEE
16 years 3 months ago
2002
IEEE
This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice le...