3120 search results - page 94 / 624 » An optimal architecture for a DDC |
146
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DAC
1997
ACM
15 years 10 months ago
1997
ACM
Abstract - This paper describes the development of a concurrent methodology for standard cell library generation. Use of a novel physical design automation method enables a high de...
156
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DAC
1994
ACM
15 years 10 months ago
1994
ACM
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these ...
175
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GLOBECOM
2009
IEEE
15 years 10 months ago
2009
IEEE
Energy efficiency has become a critical concern in designing high speed packet classification engines for next generation routers. Although TCAM-based solutions can provide high th...
179
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TOG
2008
15 years 6 months ago
2008
We present an interactive system for generating photorealistic, textured, piecewise-planar 3D models of architectural structures and urban scenes from unordered sets of photograph...
216
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TVLSI
2008
2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
15 years 6 months ago
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...