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» An optimal architecture for a DDC
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ICPP
2008
IEEE
16 years 19 days ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...
NOMS
2008
IEEE
16 years 17 days ago
Optimizing request denial and latency in an agent-based VPN architecture
—Agent-based virtual private networks architecture (ABVA) refers to the environment where a third-party provider runs and administers remote access VPN service for organizations ...
Haiyang Qian, Steve Dispensa, Deep Medhi
IEEEPACT
2002
IEEE
15 years 11 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
IPCCC
2007
IEEE
16 years 15 days ago
Optimal Cluster Head Selection in the LEACH Architecture
LEACH (Low Energy Adaptive Clustering Hierarchy) [1] is one of the popular cluster-based structures, which has been widely proposed in wireless sensor networks. LEACH uses a TDMA ...
Haiming Yang, Biplab Sikdar
ICRA
2003
IEEE
111views Robotics» more  ICRA 2003»
15 years 11 months ago
Multi-robot task allocation: analyzing the complexity and optimality of key architectures
— Important theoretical aspects of multi-robot coordination mechanisms have, to date, been largely ignored. To address part of this negligence, we focus on the problem of multi-r...
Brian P. Gerkey, Maja J. Mataric